Top 350+ Solved Digital Logic Circuits (DLC) MCQ Questions Answer
Q. The systematic reduction of logic circuits is accomplished by:
a. symbolic reduction
b. ttl logic
c. using boolean algebra
d. using a truth table
Q. Each “1” entry in a K-map square represents:
a. a high for each input truth table condition that produces a high output
b. a high output on the truth table for all low input combinations
c. a low output for all possible high input conditions
d. a don’t care condition for all possible input truth table combinations
Q. Each “0” entry in a K-map square represents:
a. a high for each input truth table condition that produces a high output
b. a high output on the truth table for all low input combinations
c. a low output for all possible high input conditions
d. a don’t care condition for all possible input truth table combinations
Q. Looping on a K-map always results in the elimination of
a. variables within the loop that appear only in their complemented form
b. variables that remain unchanged within the loop
c. variables within the loop that appear in both complemented and uncomplemented form
d. variables within the loop that appear only in their uncomplemented form
Q. Which of the following expressions is in the sum-of-products form?
a. (a + b)(c + d)
b. (a * b)(c * d)
c. a* b *(cd)
d. a * b + c * d
Q. What is an ambiguous condition in a NAND based S’-R’ latch?
a. s’=0, r’=1
b. s’=1, r’=0
c. s’=1, r’=1
d. s’=0, r’=0
Q. In a NAND based S’-R’ latch, if S’=1 & R’=1 then the state of the latch is
a. no change
b. set
c. reset
d. forbidden
Q. A NAND based S’-R’ latch can be converted into S-R latch by placing
a. a d latch at each of its input
b. an inverter at each of its input
c. it can never be converted
d. both a d latch and an inverter at its input
Q. The difference between a flip-flop & latch is
a. both are same
b. flip-flop consist of an extra output
c. latches has one input but flip-flop has two
d. latch has two inputs but flip-flop has one
Q. The S-R flip flop consist of
a. 4 and gates
b. two additional and gates
c. an additional clock input
d. 3 and gates
Q. What is one disadvantage of an S-R flip-flop?
a. it has no enable input
b. it has a race condition
c. it has no clock input
d. invalid state
Q. One example of the use of an S-R flip-flop is as
a. racer
b. stable oscillator
c. binary storage register
d. transition pulse generator
Q. When is a flip-flop said to be transparent?
a. when the q output is opposite the input
b. when the q output follows the input
c. when you can see through the ic packaging
d. when the q output is complementary of the input
Q. On a positive edge-triggered S-R flip-flop, the outputs reflect the input condition when
a. the clock pulse is low
b. the clock pulse is high
c. the clock pulse transitions from low to high
d. the clock pulse transitions from high to low