Top 350+ Solved Digital Logic Circuits (DLC) MCQ Questions Answer

From 16 to 30 of 340

Q. Hold time is the time needed for the data to after the edge of the clock is triggered.

a. decrease

b. increase

c. remain constant

d. negate

  • c. remain constant

Q. Simulator enters in which phase after the initialization phase?

a. execution phase

b. compilation phase

c. elaboration phase

d. simulation phase

  • a. execution phase

Q. The role of the is to convert the collector current into a voltage in RTL.

a. collector resistor

b. base resistor

c. capacitor

d. inductor

  • a. collector resistor

Q. The limitations of the one transistor RTL NOR gate are overcome by                      

a. two-transistor rtl implementation

b. three-transistor rtl implementation

c. multi-transistor rtl implementation

d. four-transistor rtl implementation

  • c. multi-transistor rtl implementation

Q. The primary advantage of RTL technology was that                      

a. it results as low power dissipation

b. it uses a minimum number of resistors

c. it uses a minimum number of transistors

d. it operates swiftly

  • c. it uses a minimum number of transistors

Q. The disadvantage of RTL is that                      

a. it uses a maximum number of resistors

b. it results in high power dissipation

c. high noise creation

d. it uses minimum number of transistors

  • b. it results in high power dissipation

Q. TTL circuits with “totem-pole” output stage minimize  

a. the power dissipation in rtl

b. the time consumption in rtl

c. the speed of transferring rate in rtl

d. propagation delay in rtl

  • a. the power dissipation in rtl

Q. UP-DOWN counter is also known as                        

a. dual counter

b. multi counter

c. multimode counter

d. two counter

  • c. multimode counter

Q. In an UP-counter, each flip-flop is triggered by                        

a. the output of the next flip-flop

b. the normal output of the preceding flip-flop

c. the clock pulse of the previous flip-flop

d. the inverted output of the preceding flip-flop

  • b. the normal output of the preceding flip-flop

Q. In DOWN-counter, each flip-flop is triggered by                        

a. the output of the next flip-flop

b. the normal output of the preceding flip-flop

c. the clock pulse of the previous flip-flop

d. the inverted output of the preceding flip-flop

  • d. the inverted output of the preceding flip-flop

Q. Binary counter that count incrementally and decrement is called                        

a. up-down counter

b. lsi counters

c. down counter

d. up counter

  • a. up-down counter

Q. Once an up-/down-counter begins its count sequence, it                        

a. starts counting

b. can be reversed

c. can’t be reversed

d. can be altered

  • d. can be altered
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