Top 350+ Solved Computer Architecture MCQ Questions Answer

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Q. The BUS busy line is used

a. to indicate the processor is busy

b. to indicate that the bus master is busy

c. to indicate the bus is already allocated

d. none of the mentioned

  • c. to indicate the bus is already allocated

Q. In Distributed arbitration, the device requesting the BUS               

a. asserts the start arbitration signal

b. sends an interrupt signal

c. sends an acknowledge signal

d. none of the mentioned

  • a. asserts the start arbitration signal

Q. How is a device selected in Distributed arbitration?

a. to connect the various devices to the cpu

b. to provide a path for communication between the processor and other devices

c. to facilitate data transfer between various devices

d. all of the mentioned

  • a. to connect the various devices to the cpu

Q. The device which starts data transfer is called                       

a. master

b. transactor

c. distributor

d. initiator

  • d. initiator

Q. In synchronous BUS, the devices get the timing signals from                       

a. timing generator in the device

b. a common clock line

c. timing signals are not used at all

d. none of the mentioned

  • b. a common clock line

Q. The delays caused in the switching of the timing signals is due to                       

a. memory access time

b. wmfc

c. propagation delay

d. processor delay

  • c. propagation delay

Q. The time for which the data is to be on the BUS is affected by                       

a. propagation delay of the circuit

b. setup time of the device

c. memory access time

d. propagation delay of the circuit & setup time of the device

  • d. propagation delay of the circuit & setup time of the device

Q. The status flags required for data transfer is present in            

a. device

b. device driver

c. interface circuit

d. none of the mentioned

  • c. interface circuit

Q. User programmable terminals that combine VDT hardware with built-in microprocessor is            

a. kips

b. pc

c. mainframe

d. intelligent terminals

  • d. intelligent terminals

Q.               is used as an intermediate to extend the processor BUS.

a. bridge

b. router

c. connector

d. gateway

  • a. bridge

Q.                   is an extension of the processor BUS.

a. scsi bus

b. usb

c. pci bus

d. none of the mentioned

  • c. pci bus

Q. What is the full form of ISA?

a. international american standard

b. industry standard architecture

c. international standard architecture

d. none of the mentioned

  • b. industry standard architecture
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