Top 350+ Solved Computer Architecture MCQ Questions Answer
Q. The sub-routine service procedure is similar to that of the interrupt service routine in
a. method of context switch
b. returning
c. process execution
d. method of context switch & process execution
Q. In memory-mapped I/O
a. the i/o devices and the memory share the same address space
b. the i/o devices have a separate address space
c. the memory and i/o devices have an associated address space
d. a part of the memory is specifically set aside for the i/o operation
Q. The usual BUS structure used to connect the I/O devices is
a. star bus structure
b. multiple bus structure
c. single bus structure
d. node to node bus structure
Q. The method which offers higher speeds of I/O transfers is
a. interrupts
b. memory mapping
c. program-controlled i/o
d. dma
Q. The signal sent to the device from the processor to the device after receiving an interrupt is
a. interrupt-acknowledge
b. return signal
c. service signal
d. permission signal
Q. The time between the receiver of an interrupt and its service is
a. interrupt delay
b. interrupt latency
c. cycle time
d. switching time
Q. What are the different modes of operation of a computer?
a. user and system mode
b. user and supervisor mode
c. supervisor and trace mode
d. supervisor, user and trace mode
Q. The instructions which can be run only supervisor mode are?
a. non-privileged instructions
b. system instructions
c. privileged instructions
d. exception instructions
Q. How is a privilege exception dealt with?
a. the program is halted and the system switches into supervisor mode and restarts the program execution
b. the program is stopped and removed from the queue
c. the system switches the mode and starts the execution of a new process
d. the system switches mode and runs the debugger
Q. The DMA differs from the interrupt mode by
a. the involvement of the processor for the operation
b. the method of accessing the i/o devices
c. the amount of data transfer possible
d. none of the mentioned
Q. The DMA transfers are performed by a control circuit called as
a. device interface
b. dma controller
c. data controller
d. overlooker
Q. In DMA transfers, the required signals and addresses are given by the
a. processor
b. device drivers
c. dma controllers
d. the program itself
Q. After the completion of the DMA transfer, the processor is notified by
a. acknowledge signal
b. interrupt signal
c. wmfc signal
d. none of the mentioned
Q. When the R/W bit of the status register of the DMA controller is set to 1.
a. read operation is performed
b. write operation is performed
c. read & write operation is performed
d. none of the mentioned
Q. The controller is connected to the
a. processor bus
b. system bus
c. external bus
d. none of the mentioned