Top 350+ Solved Computer Architecture MCQ Questions Answer
Q. In a general 8-bit parallel interface, the INTR line is connected to
a. status and control unit
b. ddr
c. register select
d. none of the mentioned
Q. The mode of transmission of data, where one bit is sent for each clock cycle is
a. asynchronous
b. parallel
c. serial
d. isochronous
Q. The transformation between the Parallel and serial ports is done with the help of
a. flip flops
b. logic circuits
c. shift registers
d. none of the mentioned
Q. The serial port is used to connect basically and processor.
a. i/o devices
b. speakers
c. printer
d. monitor
Q. The memory which is used to store the copy of data or instructions stored in larger memories, inside the CPU is called
a. level 1 cache
b. level 2 cache
c. registers
d. tlb
Q. The larger memory placed between the primary cache and the memory is called
a. level 1 cache
b. level 2 cache
c. eeprom
d. tlb
Q. The next level of memory hierarchy after the L2 cache is
a. secondary storage
b. tlb
c. main memory
d. register
Q. The last on the hierarchy scale of memory devices is
a. main memory
b. secondary memory
c. tlb
d. flash drives
Q. The reason for the implementation of the cache memory is
a. to increase the internal memory of the system
b. the difference in speeds of operation of the processor and memory
c. to reduce the memory access and cycle time
d. all of the mentioned
Q. The effectiveness of the cache memory is based on the property of
a. locality of reference
b. memory localisation
c. memory size
d. none of the mentioned
Q. The temporal aspect of the locality of reference means
a. that the recently executed instruction won’t be executed soon
b. that the recently executed instruction is temporarily not referenced
c. that the recently executed instruction will be executed soon again
d. none of the mentioned