Top 350+ Solved Digital Logic Circuits (DLC) MCQ Questions Answer

a. use of complementary mosfet

b. use of silicon nitride

c. using thin film technology

d. increasing potential of the channel

a. ceramic gate

b. silicon dioxide

c. silicon nitride

d. poly silicon gate

a. mosfet has low packing density

b. mosfet has medium packing density

c. mosfet has high packing density

d. mosfet has no packing density

a. high

b. low

c. neutral

d. very high

a. lsi

b. vlsi

c. msi

d. both lsi and vlsi

a. 1

b. 2

c. 3

d. 4

a. 2

b. 3

c. 4

d. 1

a. s-r

b. j-k

c. t

d. s-k

a. 0

b. 1

c. forbidden

d. toggle

a. the output toggles if one of the inputs is held high

b. only one of the inputs can be high at a time

c. the output complement follows the input when enabled

d. q output follows the input d when the enable is high

a. the q output follows the d input when en is low

b. the q output is opposite the d input when en is low

c. the q output follows the d input when en is high

d. the q output is high regardless of en’s input state

a. the output toggles if one of the inputs is held high

b. q output follows the input d when the enable is high

c. only one of the inputs can be high at a time

d. the output complement follows the input when enabled

a. if both inputs are high, the output will toggle

b. the output will follow the input on the leading edge of the clock

c. when both inputs are low, an invalid state exists

d. the input is toggled into the flip-flop on the leading edge of the clock and is passed to the output on the trailing edge of the clock

a. the d input is high and the clock transitions from high to low

b. the d input is high and the clock transitions from low to high

c. the d input is high and the clock is low

d. the d input is high and the clock is high

a. due to its capability to receive data from flip-flop

b. due to its capability to store data in flip-flop

c. due to its capability to transfer the data into flip-flop

d. due to erasing the data from the flip-flop