Top 350+ Solved Digital Electronics and Logic Design MCQ Questions Answer
Q. Looping on a K-map always results in the elimination of:
a. variables within the loop that appear only in their complemented form.
b. variables that remain unchanged within the loop.
c. variables within the loop that appear in both complemente d and uncompleme nted form.
d. variables within the loop that appear only in their uncomple mented form.
Q. What will a design engineer do after he/she is satisfied that the design will work?
a. put it in a flow chart
b. program a chip and test it
c. give the design to a technician to verify the design
d. perform a vector test
Q. What is the indication of a short on the input of a load gate?
a. only the output of the defective gate is affected.
b. there is a signal loss to all gates on the node.
c. the affected node will be stuck in the low state.
d. there is a signal loss to all gates on the node, and the affected node will be stuck in thelow state.
Q. In HDL, LITERALS is/are:
a. digital systems.
b. scalars.
c. binary coded decimals.
d. a numbering system.
Q. Which of the following expressions is in the sum-of-products form?
a. (a + b )(c + d )
b. (ab )(cd )
c. ab (cd )
d. ab + cd
Q. The 7447A is a BCD-to-7-segment decoder with ripple blanking input and output functions. The purpose of these lines is to .
a. turn off the display for any nonsignificant digit
b. turn off the display for any zero
c. turn off the display for leading or trailing zeros
d. test the display to assure all segments are operationa l
Q. One reason for using the sum-of-products form is that it can be implemented using all gates without much difficulty.
a. nor
b. nand
c. and
d. door
Q. When an open occurs on the input of a CMOS gate, the output will .
a. go low, because there is no current in an open circuit
b. react as if the open input were a high
c. go high,since full voltage appears across an open
d. be unpredicta ble; it may go high or low
Q. To subtract a signed number (the subtrahend) from another signed number (the minuend) in the 2's complement system, the minuend is .
a. complemented only if it is positive
b. complemente d only if it is negative
c. always complemente d
d. never compleme nted
Q. In an odd-parity system, the data that will produce a parity bit = 1 is .
a. data = 1010011
b. data = 1111000
c. data = 1100000
d. all of the above
Q. The addition of two signed numbers in the 2's complement system can cause overflow. For overflow to occur both numbers must .
a. be positive
b. be negative
c. have the same sign
d. have opposite signs
Q. A Karnaugh map will .
a. eliminate the need for tedious boolean simplifications
b. allow any circuit to be implemented with just and and or gates
c. produce the simplest sum-of- products expression
d. give an overall picture of how the signals flow through the logic circuit
Q. An 8-bit binary number is input to an odd parity generator. The parity bit will equal 1 only if .
a. the number is odd
b. the number of 1s in the number is odd
c. the number is even
d. the number of 1s in the number is even
Q. Two 4-bit comparators are cascaded to form an 8-bit comparator. The cascading inputs of the most significant 4 bits should be connected.
a. to the outputs from the least significant 4- bit comparator
b. to the cascading inputs of the least significant 4- bit comparator
c. a = b to a logic high, a< b and a > b to a logic low
d. ground
Q. When Karnaugh mapping, we must be sure to use the number of loops.
a. maximum
b. minimum
c. median
d. karnaugh