Top 350+ Solved Digital Electronics and Logic Design MCQ Questions Answer

From 166 to 180 of 469

Q. The final output of a POS circuit is generated by .

a. an and

b. an or

c. a nor

d. a nand

  • a. an and

Q. The circuit produces a HIGH output whenever the two inputs are equal.

a. exclusive-and

b. exclusive- nand

c. exclusive- nor

d. exclusive- or

  • c. exclusive- nor

Q. The statement evaluates the variable status.

a. if/then

b. if/then/el se

c. case

d. elsif

  • a. if/then

Q. In VHDL, data can be each of the following types except .

a. bit

b. bit_vector

c. std_logic

d. std_vect or

  • d. std_vect or

Q. When grouping cells within a K-map, the cells must be combined in groups of .

a. 2\s

b. 1, 2, 4, 8, etc.

c. 4\s

d. 3\s

  • b. 1, 2, 4, 8, etc.

Q. The circuit produces a HIGH output whenever the two inputs are unequal.

a. exclusive-and

b. exclusive- nor

c. exclusive-or

d. inexclusive-or

  • c. exclusive-or

Q. The carry output of each adder in a ripple adder provides an additional sum output bit.

a. true

b. false

c. none of the above

d. can not predict

  • a. true

Q. Truth tables are great for listing all possible combinations of independent variables.

a. true

b. false

c. none of the above

d. can not predict

  • a. true

Q. To implement the full-adder sum functions, two exclusive-OR gates can be used.

a. true

b. false

c. none of the above

d. can not predict

  • a. true
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