Top 350+ Solved Computer Architecture MCQ Questions Answer
Q. The advantage of I/O mapped devices to memory mapped is ___________
a. The former offers faster transfer of data
b. The devices connected using I/O mapping have a bigger buffer space
c. The devices have to deal with fewer address lines
d. No advantage as such
Q. The system is notified of a read or write operation by ___________
a. Appending an extra bit of the address
b. Enabling the read or write bits of the devices
c. Raising an appropriate interrupt signal
d. Sending a special signal along the BUS
Q. To overcome the lag in the operating speeds of the I/O device and the processor we use ___________
a. Buffer spaces
b. Status flags
c. Interrupt signals
d. Exceptions
Q. The method which offers higher speeds of I/O transfers is ___________
a. Interrupts
b. Memory mapping
c. Program-controlled I/O
d. DMA
Q. The instruction, Add #45, R1 does _______
a. Adds the value of 45 to the address of R1 and stores 45 in that address
b. Adds 45 to the value of R1 and stores it in R1
c. Finds the memory location 45 and adds that content to that of R1
d. None of the mentioned
Q. In the case of, Zero-address instruction method the operands are stored in _____
a. Registers
b. Accumulators
c. Push down stack
d. Cache
Q. The addressing mode which makes use of in-direction pointers is ______
a. Indirect addressing mode
b. Index addressing mode
c. Relative addressing mode
d. Offset addressing mode
Q. The addressing mode/s, which uses the PC instead of a general purpose register is ______
a. Indexed with offset
b. Relative
c. direct
d. both Indexed with offset and direct
Q. _____ addressing mode is most suitable to change the normal sequence of execution of instructions.
a. Relative
b. Indirect
c. Index with Offset
d. Immediate
Q. The reason for the implementation of the cache memory is ________
a. To increase the internal memory of the system
b. The difference in speeds of operation of the processor and memory
c. To reduce the memory access and cycle time
d. All of the mentioned
Q. The effectiveness of the cache memory is based on the property of ________
a. Locality of reference
b. Memory localisation
c. Memory size
d. None of the mentioned
Q. The spatial aspect of the locality of reference means ________
a. That the recently executed instruction is executed again next
b. That the recently executed won’t be executed again
c. That the instruction executed will be executed at a later time
d. That the instruction in close proximity of the instruction executed will be executed in future
Q. The correspondence between the main memory blocks and those in the cache is given by _________
a. Hash function
b. Mapping function
c. Locale function
d. Assign function
Q. The copy-back protocol is used ________
a. To copy the contents of the memory onto the cache
b. To update the contents of the memory from the cache
c. To remove the contents of the cache and push it on to the memory
d. None of the mentioned
Q. The address space is 22 bits the memory is 32 bit word addressable what is the memory size
a. 16MB
b. 512KB
c. 4MB
d. 1GB