Top 350+ Solved Computer Architecture MCQ Questions Answer
Q. Every time a new instruction is loaded into IR the output of is loaded into UPC.
a. starting address generator
b. loader
c. linker
d. clock
Q. The case/s where micro-programmed can perform well
a. when it requires to check the condition codes
b. when it has to choose between the two alternatives
c. when it is triggered by an interrupt
d. none of the mentioned
Q. is used to implement virtual memory organisation.
a. page table
b. frame table
c. mmu
d. none of the mentioned
Q. translates the logical address into a physical address.
a. mmu
b. translator
c. compiler
d. linker
Q. The fetch and execution cycles are interleaved with the help of ________
a. Modification in processor architecture
b. Clock
c. Special unit
d. Control unit
Q. To increase the speed of memory access in pipelining, we make use of _______
a. Special memory locations
b. Special purpose registers
c. Cache
d. Buffers
Q. The situation wherein the data of operands are not available is called ______
a. Data hazard
b. Stock
c. Deadlock
d. Structural hazard
Q. The time lost due to the branch instruction is often referred to as _____
a. Latency
b. Delay
c. Branch penalty
d. None of the mentioned
Q. The algorithm followed in most of the systems to perform out of order execution is ______
a. Tomasulo algorithm
b. Score carding
c. Reader-writer algorithm
d. None of the mentioned
Q. The logic operations are implemented using _______ circuits.
a. Bridge
b. Logical
c. Combinatorial
d. Gate
Q. The carry generation function: ci + 1 = yici + xici + xiyi, is implemented in ____________
a. Half adders
b. Full adders
c. Ripple adders
d. Fast adders
Q. Which option is true regarding the carry in the ripple adders?
a. Are generated at the beginning only
b. Must travel through the configuration
c. Is generated at the end of each operation
d. None of the mentioned
Q. In full adders the sum circuit is implemented using ________
a. And & or gates
b. NAND gate
c. XOR
d. XNOR
Q. The usual implementation of the carry circuit involves _________
a. And & or gates
b. XOR
c. NAND
d. XNOR