Top 150+ Solved Muli-core Architectures and Programming MCQ Questions Answer
Q. A collection of lines that connects several devices is called ______________
a. bus
b. peripheral connection wires
c. Both a and b
d. internal wires
Q. PC Program Counter is also called ____________
a. instruction pointer
b. memory pointer
c. data counter
d. file pointer
Q. Which MIMD systems are best scalable with respect to the number ofprocessors?
a. Distributed memory computers
b. ccNUMA systems
c. nccNUMA systems
d. Symmetric multiprocessors
Q. Cache coherence: For which shared (virtual) memory systems is the snooping protocol suited?
a. Crossbar connected systems
b. Systems with hypercube network
c. Systems with butterfly network
d. Bus based systems
Q. The idea of cache memory is based ______
a. on the property of locality of reference
b. on the heuristic 90-10 rule
c. on the fact that references generally tend to cluster
d. all of the above
Q. When number of switch ports is equal to or larger than number of devices,this simple network is referred to as ______________
a. Crossbar
b. Crossbar switch
c. Switching
d. Both a and b
Q. A remote node is being node which has a copy of a ______________
a. Home block
b. Guest block
c. Remote block
d. Cache block
Q. A pipeline is like _______________
a. an automobile assembly line
b. house pipeline
c. both a and b
d. a gas line
Q. Which cache miss does not occur in case of a fully associative cache?
a. Conflict miss
b. Capacity miss
c. Compulsory miss
d. Cold start miss
Q. Bus switches are present in ____________
a. bus window technique
b. crossbar switching
c. linked input/output
d. shared bus
Q. Systems that do not have parallel processing capabilities are ______________
a. SISD
b. MIMD
c. SIMD
d. MISD
Q. SIMD represents an organization that ______________
a. Includes many processing units under the supervision of a common control unit
b. vector supercomputer and MIMD systems
c. logic behind pipelining an instruction as observe
d. receive an instruction from the controlling unit
Q. Cache memory works on the principle of ____________
a. communication links
b. Locality of reference
c. Bisection bandwidth
d. average access time
Q. In shared bus architecture, the required processor(s) to perform a bus cycle, for fetching data or instructions is ________________
a. One Processor
b. Two Processor
c. Multi-Processor
d. None of the above