Top 550+ Solved Digital Principles and System Design MCQ Questions Answer
Q. The output of latches will remain in set/reset untill
a. the trigger pulse is given to change the state
b. any pulse given to go into previous state
c. they don’t get any pulse more
d. the pulse is edge-triggered
Q. What is a trigger pulse?
a. a pulse that starts a cycle of operation
b. a pulse that reverses the cycle of operation
c. a pulse that prevents a cycle of operation
d. a pulse that enhances a cycle of operation
Q. The circuits of NOR based S-R latch classified as asynchronous sequential circuits, why?
a. because of inverted outputs
b. because of triggering functionality
c. because of cross-coupled connection
d. because of inverted outputs & triggering functionality
Q. A latch is an example of a
a. monostable multivibrator
b. astable multivibrator
c. bistable multivibrator
d. 555 timer
Q. Latch is a device with
a. one stable state
b. two stable state
c. three stable state
d. infinite stable states
Q. Why latches are called a memory devices?
a. it has capability to stare 8 bits of data
b. it has internal memory of 4 bit
c. it can store one bit of data
d. it can store infinite amount of data
Q. Two stable states of latches are
a. astable & monostable
b. low input & high output
c. high output & low output
d. low output & high input
Q. The first step of analysis procedure of SR latch is to
a. label inputs
b. label outputs
c. label states
d. label tables
Q. When a high is applied to the Set line of an SR latch, then
a. q output goes high
b. q’ output goes high
c. q output goes low
d. both q and q’ go high
Q. When both inputs of SR latches are low, the latch
a. q output goes high
b. q’ output goes high
c. it remains in its previously set or reset state
d. it goes to its next set or reset state