Top 350+ Solved Digital Electronics and Logic Design MCQ Questions Answer
Q. The range of a valid LOW input is:
a. 0.0 v to 0.4 v
b. 0.4 v to 0.8 v
c. 0.0 v to 1.8 v
d. 0.0 v to2.8 v
Q. When an IC has two rows of parallel connecting pins, the device is referred to as:
a. a qfp
b. a dip
c. a phase splitter
d. cmos
Q. Which digital IC package type makes the most efficient use of printed circuit board space?
a. smt
b. to can
c. flat pack
d. dip
Q. The digital logic family which has the lowest propagation delay time is
a. ecl
b. ttl
c. cmos
d. pmos
Q. Which TTL logic gate is used for wired ANDing
a. open collector output
b. totem pole
c. tri state output
d. ecl gates
Q. In a positive logic system, logic state 1 corresponds to
a. positive voltage
b. higher voltage level
c. zero voltage level
d. lower voltage level
Q. The commercially available 8-input multiplexer integrated circuit in the TTL family is
a. 7495
b. 74153
c. 74154
d. 74151
Q. The logic 0 level of a CMOS logic device is approximately
a. 1.2 volts
b. 0.4 volts
c. 0volts
d. 5volts
Q. How is the noise margin of a logic family defi ned?
a. voh – vol
b. greater of vdd – vohand vol – gnd
c. smaller of vil – voland voh – vih
d. vih – vil.
Q. What parameter causes the main limit on fan-out of CMOS logic in high-speed applications?
a. d.c. input current
b. output current
c. input capacitance
d. power supply voltage.
Q. The number of standard loads that the output of the gate can drive with out impairment of its normal operation is
a. fan-in
b. fan-out
c. noise-margin
d. power- dissipiatio n