Top 250+ Solved High Performance Computing (HPC) MCQ Questions Answer

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Q. CUDA provides ------- warp and thread scheduling. Also, the overhead of thread creation is on the order of ----.

a. “programming-overhead”, 2 clock

b. “zero-overhead”, 1 clock

c. 64, 2 clock

d. 32, 1 clock

  • b. “zero-overhead”, 1 clock

Q. Each warp of GPU receives a single instruction and “broadcasts” it to all of its threads. It is a ---- operation.

a. simd (single instruction multiple data)

b. simt (single instruction multiple thread)

c. sisd (single instruction single data)

d. sist (single instruction single thread)

  • b. simt (single instruction multiple thread)

Q. Limitations of CUDA Kernel

a. recursion, call stack, static variable declaration

b. no recursion, no call stack, no static variable declarations

c. recursion, no call stack, static variable declaration

d. no recursion, call stack, no static variable declarations

  • b. no recursion, no call stack, no static variable declarations

Q. What is Unified Virtual Machine

a. it is a technique that allow both cpu and gpu to read from single virtual machine, simultaneously.

b. it is a technique for managing separate host and device memory spaces.

c. it is a technique for executing device code on host and host code on device.

d. it is a technique for executing general purpose programs on device instead of host.

  • a. it is a technique that allow both cpu and gpu to read from single virtual machine, simultaneously.

Q. _______ became the first language specifically designed by a GPU Company to facilitate general purpose computing on ____.

a. python, gpus.

b. c, cpus.

c. cuda c, gpus.

d. java, cpus.

  • c. cuda c, gpus.

Q. The CUDA architecture consists of --------- for parallel computing kernels and functions.

a. risc instruction set architecture

b. cisc instruction set architecture

c. zisc instruction set architecture

d. ptx instruction set architecture

  • d. ptx instruction set architecture

Q. CUDA stands for --------, designed by NVIDIA.

a. common union discrete architecture

b. complex unidentified device architecture

c. compute unified device architecture

d. complex unstructured distributed architecture

  • c. compute unified device architecture

Q. NVIDIA 8-series GPUs offer -------- .

a. 50-200 gflops

b. 200-400 gflops

c. 400-800 gflops

d. 800-1000 gflops

  • a. 50-200 gflops

Q. IADD, IMUL24, IMAD24, IMIN, IMAX are ----------- supported by Scalar Processors of NVIDIA GPU.

a. 32-bit ieee floating point instructions

b. 32-bit integer instructions

c. both

d. none of the above

  • b. 32-bit integer instructions

Q. What is the equivalent of general C program with CUDA C: int main(void) { printf("Hello, World!\n"); return 0; }

a. int main ( void ) { kernel <<<1,1>>>(); printf("hello, world!\\n"); return 0; }

b. __global__ void kernel( void ) { } int main ( void ) { kernel <<<1,1>>>(); printf("hello, world!\\n"); return 0; }

c. __global__ void kernel( void ) { kernel <<<1,1>>>(); printf("hello, world!\\n"); return 0; }

d. __global__ int main ( void ) { kernel <<<1,1>>>(); printf("hello, world!\\n"); return 0; }

  • b. __global__ void kernel( void ) { } int main ( void ) { kernel <<<1,1>>>(); printf("hello, world!\\n"); return 0; }
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