Top 550+ Solved Digital Principles and System Design MCQ Questions Answer
Q. In a digital clock application, the basic frequency must be divided down as
a. 1 hz
b. 60 hz
c. 100 hz
d. 1000 hz
Q. What does the data signal do in the keypad application?
a. the row and column encoded data
b. the ring encoded data
c. the freeze locator data
d. the ring counter data
Q. When a key is pressed, what does the ring counter in the HDL keypad application do?
a. count to find the row
b. freeze
c. count to find the column
d. start the d flip-flop
Q. A step which should be followed in project management is known as
a. overall definition
b. system documentation
c. synthesis and testing
d. system integration
Q. In the keypad application, the preset state of the ring counter define
a. the nanding of the columns
b. the nanding of the rows
c. the proper output of the column encoder
d. the proper output of the row encoder
Q. A major block which is not a part of an HDL frequency counter
a. timing and control unit
b. decoder/display
c. display register
d. bit shifter
Q. A stepper motor HDL application must include
a. sequencers and multiplexers
b. types and bits
c. counters and decoders
d. variables and processes
Q. Which of the following is a not a characteristics of combinational circuits?
a. the output of combinational circuit depends on present input
b. there is no use of clock signal in combinational circuits
c. the output of combinational circuit depends on previous output
d. there is no storage element in combinational circuit
Q. A 4 to 16 decoder can be used as a code converter. What will be the inputs and outputs of the converter respectively?
a. binary, octal
b. octal, binary
c. hexadecimal, binary
d. binary, hexadecimal
Q. Latches constructed with NOR and NAND gates tend to remain in the latched condition due to which configuration feature?
a. low input voltages
b. synchronous operation
c. gate impedance
d. cross coupling
Q. One example of the use of an S-R flip-flop is as
a. transition pulse generator
b. racer
c. switch debouncer
d. astable oscillator
Q. When both inputs of a J-K flip-flop cycle, the output will
a. be invalid
b. change
c. not change
d. toggle
Q. Which of the following is correct for a gated D-type flip-flop?
a. the q output is either set or reset as soon as the d input goes high or low
b. the output complement follows the input when enabled
c. only one of the inputs can be high at a time
d. the output toggles if one of the inputs is held high
Q. A basic S-R flip-flop can be constructed by cross- coupling of which basic logic gates?
a. and or or gates
b. xor or xnor gates
c. nor or nand gates
d. and or nor gates