Top 350+ Solved Digital Electronics and Logic Design MCQ Questions Answer
Q. Most demultiplexers facilitate which of the following?
a. decimal to hexadecimal
b. single input, multiple outputs
c. ac to dc
d. odd parity to even parity
Q. One application of a digital multiplexer is to facilitate:
a. code conversion
b. parity checking
c. parallel-to- serial data conversion
d. data generation
Q. Select one of the following statements that best describes the parity method of error detection:
a. best suited for detecting single-bit errors in transmitted codes.
b. best suited for detecting double-bit errors that occur during the transmission of codes from one location to another.
c. a and b
d. none of the above
Q. A multiplexed display:
a. accepts data inputs from one line and passes this data to multiple output lines
b. uses one display to present two or more pieces of information
c. accepts data inputs from multiple lines and passes this data to multiple output lines
d. accepts data inputs from several lines and multiplexe s this input data to four bcd lines
Q. In which of the following gates, the output is 1, if and only if at least one input is 1?
a. nor
b. and
c. or
d. nand
Q. The time required for a gate or inverter to change its state is called
a. rise time iz
b. decay time
c. propagation time
d. charging time
Q. The time required for a pulse to change from 10 to 90 percent of its maximum value is called
a. rise time iz
b. decay time
c. propagation time
d. operating speed
Q. The maximum frequency at which digital data can be applied to gate is called
a. operating speed
b. propagation speed
c. binary level transaction period
d. charging time
Q. What is the minimum number of two-input NAND gates used to perform the function of two input OR gate ?
a. one
b. two
c. three
d. four
Q. The time required for a pulse to decrease from 90 to 10 per cent of its maximum value is called
a. rise time
b. decay time
c. binary level transition period
d. propagatio n delay
Q. Which of the following gates would output 1 when one input is 1 and other input is 0 ?
a. or gate
b. and gate
c. nand gate
d. and gate
Q. Which of the following expressions is not equivalent to X ' ?
a. x nand x
b. x nor x
c. x nand 1
d. x nor 1
Q. Which of the following gates are added to the inputs of the OR gate to convert it to the NAND gate ?
a. not
b. and
c. or
d. xor
Q. The EXCLUSIVE NOR gate is equivalent to which gate followed by an inverter ?
a. or gate
b. and
c. nand
d. xor
Q. Which of the following gates is known as coincidence detector ?
a. and gate
b. or gate
c. not gate
d. nand gate