Top 150+ Solved Computer Organization and Architecture MCQ Questions Answer

From 76 to 90 of 140

Q. A register capable of shifting its binary information either to the right or the left is called a

a. parallel register.

b. serial register.

c. shift register.

d. storage register.

  • c. shift register.

Q. What is the content of Stack Pointer (SP)?

a. Address of the current instruction

b. Address of the next instruction

c. Address of the top element of the stack

d. Size of the stack.

  • c. Address of the top element of the stack

Q. Which of the following interrupt is non maskable

a. INTR.

b. RST 7.5.

c. RST 6.5.

d. TRAP.

  • d. TRAP.

Q. Which of the following is a main memory

a. Secondary memory.

b. Auxiliary memory.

c. Cache memory.

d. Virtual memory.

  • c. Cache memory.

Q. Which of the following are not a machine instructions

a. MOV.

b. ORG.

c. END.

d. (B) & (C) .

  • d. (B) & (C) .

Q. The memory unit that communicates directly with the CPU is called the

a. main memory

b. Secondary memory

c. shared memory

d. auxiliary memory.

  • a. main memory

Q. The average time required to reach a storage location in memory and obtain itscontents is called

a. Latency time.

b. Access time.

c. Turnaround time.

d. Response time.

  • b. Access time.

Q. A successive A/D converter is

a. a high-speed converter.

b. a low speed converter.

c. a medium speed converter.

d. none of these.

  • c. a medium speed converter.

Q. When necessary, the results are transferred from the CPU to main memory by

a. I/O devices.

b. CPU.

c. shift registers.

d. none of these.

  • c. shift registers.

Q. A combinational logic circuit which sends data coming from a single source to twoor more separate destinations is

a. Decoder.

b. Encoder.

c. Multiplexer.

d. Demultiplexer.

  • d. Demultiplexer.

Q. In which addressing mode the operand is given explicitly in the instruction

a. Absolute.

b. Immediate .

c. Indirect.

d. Direct.

  • b. Immediate .

Q. A stack organized computer has

a. Three-address Instruction.

b. Two-address Instruction.

c. One-address Instruction.

d. Zero-address Instruction.

  • d. Zero-address Instruction.
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