Top 350+ Solved Digital Electronics MCQ Questions Answer
Q. A latch is an example of a
a. monostable multivibrator
b. astable multivibrator
c. bistable multivibrator
d. 555 timer
Q. Latch is a device with
a. one stable state
b. two stable state
c. three stable state
d. infinite stable states
Q. Why latches are called a memory devices?
a. it has capability to stare 8 bits of data
b. it has internal memory of 4 bit
c. it can store one bit of data
d. it can store infinite amount of data
Q. Two stable states of latches are
a. astable & monostable
b. low input & high output
c. high output & low output
d. low output & high input
Q. The first step of analysis procedure of SR latch is to
a. label inputs
b. label outputs
c. label states
d. label tables
Q. When a high is applied to the Set line of an SR latch, then
a. q output goes high
b. q’ output goes high
c. q output goes low
d. both q and q’ go high
Q. When both inputs of SR latches are low, the latch
a. q output goes high
b. q’ output goes high
c. it remains in its previously set or reset state
d. it goes to its next set or reset state
Q. When both inputs of SR latches are high, the latch goes
a. unstable
b. stable
c. metastable
d. bistable
Q. Which of the following logic families has the highest maximum clock frequency?
a. s-ttl
b. as-ttl
c. hs-ttl
d. hcmos
Q. Why is the fan-out of CMOS gates frequency dependent?
a. each cmos input gate has a specific propagation time and this limits the number of different gates that can be connected to the output of a cmos gate
b. when the frequency reaches the critical value the gate will only be capable of delivering 70% of the normal output voltage and consequently the output power will be one-half of normal and this defines the upper operating frequency
c. the higher number of gates attached to the output the more frequently they will have to be serviced thus reducing the frequency at which each will be serviced with an input signal
d. the input gates of the fets are predominantly capacitive and as the signal frequency increases the capacitive loading also increases thereby limiting the number of loads that may be attached to the output of the driving gate