Top 350+ Solved Digital Electronics MCQ Questions Answer
Q. Which term applies to the maintaining of a given signal level until the next sampling?
a. holding
b. aliasing
c. shannon frequency sampling
d. "stair-stepping"
Q. An op-amp has very ________.
a. high voltage gain
b. high input impedance
c. low output impedance
d. all of the above
Q. The dual-slope analog-to-digital converter finds extensive use in ________.
a. digital voltmeters
b. function generators
c. frequency counters
d. all of the above
Q. The ADC0804 is an example of a ________.
a. single-slope analog-to-digital converter
b. dual-slope analog-to-digital converter
c. digital-ramp analog-to-digital converter
d. successive-approximation analog-to-digital converter
Q. In a digital representation of voltages using an 8-bit binary code, how many values can be defined?
a. 16
b. 64
c. 128
d. 256
Q. A 4-bit R/2R ladder digital-to-analog converter uses ________.
a. one resistor value
b. two resistor values
c. three resistor values
d. four resistor values
Q. How are unwanted frequencies removed prior to digital conversion?
a. pre-filters
b. digital signal processing
c. sample-and-hold circuits
d. all of the above
Q. Which type of programming is typically used for digital signal processors?
a. assembly language
b. machine language
c. c
d. none of the above
Q. Which of the following best defines Nyquist frequency?
a. the frequency of resonance for the filtering circuit
b. the second harmonic
c. the lower frequency limit of sampling
d. the highest frequency component of a given analog signal
Q. Which is not an A/D conversion error?
a. differential nonlinearity
b. missing code
c. incorrect code
d. offset
Q. Settling time is normally defined as the time it takes a DAC to settle within ________.
a. 1/8 lsb of its final value when a change occurs in the input code
b. 1/4 lsb of its final value when a change occurs in the input code
c. 1/2 lsb of its final value when a change occurs in the input code
d. 1 lsb of its final value when a change occurs in the input code
Q. Determine the output frequency for a frequency division circuit that contains 12 flip-flops with an input clock frequency of 20.48 MHz.
a. 10.24 khz
b. 5 khz
c. 30.24 khz
d. 15 khz
Q. Which statement BEST describes the operation of a negative-edge-triggered D flip-flop?
a. the logic level at the d input is transferred to q on ngt of clk.
b. the q output is always identical to the clk input if the d input is high.
c. the q output is always identical to the d input when clk = pgt.
d. the q output is always identical to the d input.